The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2006

Filed:

Aug. 03, 2004
Applicants:

Xiaomei Bu, Singapore, SG;

Alex See, Singapore, SG;

Tae Jong Lee, Singapore, SG;

Fan Zhang, Singapore, SG;

Yeon Kheng Lim, Singapore, SG;

Liang Choo Hsia, Singapore, SG;

Inventors:

Xiaomei Bu, Singapore, SG;

Alex See, Singapore, SG;

Tae Jong Lee, Singapore, SG;

Fan Zhang, Singapore, SG;

Yeon Kheng Lim, Singapore, SG;

Liang Choo Hsia, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/46 (2006.01); H01L 21/78 (2006.01); H01L 21/301 (2006.01); H01L 21/76 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.


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