The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2006
Filed:
Aug. 11, 2004
Hyungjun Park, Paju-Si, KR;
Hyeongno Kim, Paju-Si, KR;
Sangbae Park, Paju-Si, KR;
Yonggil Lee, Paju-Si, KR;
Kyungsoo Rho, Paju-Si, KR;
Junyoung Yang, Paju-Si, KR;
Jinhee Won, Paju-Si, KR;
HyungJun Park, Paju-Si, KR;
HyeongNo Kim, Paju-Si, KR;
SangBae Park, Paju-Si, KR;
YongGil Lee, Paju-Si, KR;
KyungSoo Rho, Paju-Si, KR;
JunYoung Yang, Paju-Si, KR;
JinHee Won, Paju-Si, KR;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. Each lead of the lead frame has a first portion, a second portion and a third portion connecting the first portion and the second portion, wherein the first metal layer is not provided on the third portion. After a wire bonding step and an encapsulating step are conducted, a second metal layer is selectively plated on the first portions and the second portions of the leads and the die pads exposed from the bottom of the molded product. Then, the third portion of each lead is selectively etched away such that the first portion and the second portion are electrically isolated from each other. Finally, a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.