The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2006
Filed:
Oct. 03, 2002
Frank D. Egitto, Binghamton, NY (US);
Elizabeth Foster, Friendsville, PA (US);
Raymond T. Galasco, Vestal, NY (US);
Voya R. Markovich, Endwell, NY (US);
Manh-quan Tam Nguyen, Endicott, NY (US);
Frank D. Egitto, Binghamton, NY (US);
Elizabeth Foster, Friendsville, PA (US);
Raymond T. Galasco, Vestal, NY (US);
Voya R. Markovich, Endwell, NY (US);
Manh-Quan Tam Nguyen, Endicott, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.