The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2006
Filed:
Mar. 05, 2004
Alex Wang, Cupertino, CA (US);
Shang-de Ted Chang, Fremont, CA (US);
Han-chih Lin, Hsin-Chu, TW;
Tzeng-huei Shiau, Hsin-Chu, TW;
I-sheng Liu, San Jose, CA (US);
Hsien-wen Liu, Taoyuan, TW;
Alex Wang, Cupertino, CA (US);
Shang-De Ted Chang, Fremont, CA (US);
Han-Chih Lin, Hsin-Chu, TW;
Tzeng-Huei Shiau, Hsin-Chu, TW;
I-Sheng Liu, San Jose, CA (US);
Hsien-Wen Liu, Taoyuan, TW;
Chingis Technology Corporation, San Jose, CA (US);
Abstract
A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.