The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2006
Filed:
Nov. 14, 2003
Chad A. Cobbley, Boise, ID (US);
John Vannortwick, Kuna, ID (US);
Bret K. Street, Meridian, ID (US);
Tongbi Jiang, Boise, ID (US);
Chad A. Cobbley, Boise, ID (US);
John VanNortwick, Kuna, ID (US);
Bret K. Street, Meridian, ID (US);
Tongbi Jiang, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using 'wet' quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using 'dry' epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.