The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2006
Filed:
Sep. 15, 2003
Ming-fang Wang, Taichung, TW;
Chia-lin Chen, Hsinchu, TW;
Chih-wei Yang, Kaohsiung, TW;
Chi-chun Chen, Kaohsiung, TW;
Tuo-hung Hou, Chia-Yi, TW;
Yeou-ming Lin, Jungli, TW;
Liang-gi Yao, Hsing-Chu, TW;
Shih-chang Chen, Taoyuan, TW;
Ming-Fang Wang, Taichung, TW;
Chia-Lin Chen, Hsinchu, TW;
Chih-Wei Yang, Kaohsiung, TW;
Chi-Chun Chen, Kaohsiung, TW;
Tuo-Hung Hou, Chia-Yi, TW;
Yeou-Ming Lin, Jungli, TW;
Liang-Gi Yao, Hsing-Chu, TW;
Shih-Chang Chen, Taoyuan, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.