The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2006

Filed:

Jun. 18, 2004
Applicants:

Jaime A. Bayan, Palo Alto, CA (US);

Ashok S. Prabhu, San Jose, CA (US);

Chan Chee Ling, Negeri Sembilan, MY;

Lye Meng Kong, Melaka, MY;

Santhiran S O Nadarajah, Melaka, MY;

Inventors:

Jaime A. Bayan, Palo Alto, CA (US);

Ashok S. Prabhu, San Jose, CA (US);

Chan Chee Ling, Negeri Sembilan, MY;

Lye Meng Kong, Melaka, MY;

Santhiran S O Nadarajah, Melaka, MY;

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
Abstract

A die attach region for use in an IC package is described. The die attach region employs a number of posts interconnected with a number of support risers to provide a structure that upholds a semiconductor die while facilitating flow of an encapsulant material underneath the die during encapsulation. The posts and risers can be arranged in a number of configurations that each facilitate flow of encapsulant material. This die attach region can be incorporated into a lead-frame structure or a substrate panel for ease and efficiency of manufacture.


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