The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2006
Filed:
Apr. 16, 2004
Kosuke Inoue, Fujisawa, JP;
Hiroyuki Tenmei, Yokohama, JP;
Yoshihide Yamaguchi, Fujisawa, JP;
Noriyuki Oroku, Yokohama, JP;
Hiroshi Hozoji, Yokohama, JP;
Shigeharu Tsunoda, Fujisawa, JP;
Madoka Minagawa, Ebina, JP;
Naoya Kanda, Fujisawa, JP;
Ichiro Anjo, Tokyo, JP;
Asao Nishimura, Tokyo, JP;
Akira Yajima, Ebina, JP;
Kenji Ujiie, Tokyo, JP;
Kosuke Inoue, Fujisawa, JP;
Hiroyuki Tenmei, Yokohama, JP;
Yoshihide Yamaguchi, Fujisawa, JP;
Noriyuki Oroku, Yokohama, JP;
Hiroshi Hozoji, Yokohama, JP;
Shigeharu Tsunoda, Fujisawa, JP;
Madoka Minagawa, Ebina, JP;
Naoya Kanda, Fujisawa, JP;
Ichiro Anjo, Tokyo, JP;
Asao Nishimura, Tokyo, JP;
Akira Yajima, Ebina, JP;
Kenji Ujiie, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide α-ray shielding of the semiconductor device.