The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2006
Filed:
Oct. 07, 2004
Michael Maldei, Durham, NC (US);
Jinhwan Lee, Cary, NC (US);
Guenter Gerstmeier, Chapel Hill, NC (US);
Brian Cousineau, Burlington, NC (US);
Jon S. Berry, Ii, Raleigh, NC (US);
Steven M. Baker, Apex, NC (US);
Malati Hedge, Cary, NC (US);
Michael Maldei, Durham, NC (US);
Jinhwan Lee, Cary, NC (US);
Guenter Gerstmeier, Chapel Hill, NC (US);
Brian Cousineau, Burlington, NC (US);
Jon S. Berry, II, Raleigh, NC (US);
Steven M. Baker, Apex, NC (US);
Malati Hedge, Cary, NC (US);
Infineon Technologies AG, Munich, DE;
Abstract
A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.