The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7035770 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 25, 2006

Filed:

Dec. 18, 2003
Applicants:

Shuo-huei Lin, Hsin-Chu, TW;

Ruenn-sheng Peng, Hsin-Chu, TW;

Yi-ju Chen, Taipei, TW;

Kuo-rung Hsiao, Hsin-Chu, TW;

Inventors:

Shuo-Huei Lin, Hsin-Chu, TW;

Ruenn-Sheng Peng, Hsin-Chu, TW;

Yi-Ju Chen, Taipei, TW;

Kuo-Rung Hsiao, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

System and method for detecting suspicious process faults. A preferred embodiment comprises determining a strength relationship between wafer acceptance test (WAT) parameters and process steps. The strength relationships indicate the affect of a failed process step on the value of a WAT parameter. Thus, if a WAT parameter is not within the parameters set in the WAT, then the suspicious process steps that caused the failure are the process steps that had a strength relationship with the failed WAT parameter. Furthermore, in a preferred embodiment, negative inferences are determined and utilized to determine a degree of suspiciousness. The degree of suspiciousness is used to determine a total degree of suspiciousness.


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Lin, Shuo-Huei. (2006). Fuzzy reasoning model for semiconductor process fault detection using wafer acceptance test data (U.S. Patent No. 7035770). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7035770

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