The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Dec. 30, 2003
Kwan-yong Lim, Kyoungki-do, KR;
Byung-seop Hong, Kyoungki-do, KR;
Heung-jae Cho, Kyoungki-do, KR;
Jung-ho Lee, Kyoungki-do, KR;
Jae-geun OH, Kyoungki-do, KR;
Yong-soo Kim, Kyoungki-do, KR;
Se-aug Jang, Kyoungki-do, KR;
Hong-seon Yang, Kyoungki-do, KR;
Hyun-chul Sohn, Kyoungki-do, KR;
Kwan-Yong Lim, Kyoungki-do, KR;
Byung-Seop Hong, Kyoungki-do, KR;
Heung-Jae Cho, Kyoungki-do, KR;
Jung-Ho Lee, Kyoungki-do, KR;
Jae-Geun Oh, Kyoungki-do, KR;
Yong-Soo Kim, Kyoungki-do, KR;
Se-Aug Jang, Kyoungki-do, KR;
Hong-Seon Yang, Kyoungki-do, KR;
Hyun-Chul Sohn, Kyoungki-do, KR;
Hynix Semiconductor Inc., Ichon-shi, KR;
Abstract
The present invention is related to a method for fabricating a transistor with a polymetal gate electrode structure. The method includes the steps of: forming a gate insulation layer on a substrate; forming a patterned gate stack structure on the gate insulation layer, wherein the patterned stack structure includes a polysilicon layer as a bottom layer and a metal layer as an upper layer; forming a silicon oxide-based capping layer along a profile containing the patterned gate stack structure and on the gate insulation layer at a predetermined temperature that prevents oxidation of the metal layer; and performing a gate re-oxidation process.