The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2006

Filed:

Nov. 04, 2003
Applicants:

Cyrus E. Tabery, Santa Clara, CA (US);

Shibly S. Ahmed, San Jose, CA (US);

Matthew S. Buynoski, Palo Alto, CA (US);

Srikanteswara Dakshina-murthy, Wappingers Falls, NY (US);

Zoran Krivokapic, Santa Clara, CA (US);

Haihong Wang, Milpitas, CA (US);

Chih-yuh Yang, San Jose, CA (US);

Bin Yu, Cupertino, CA (US);

Inventors:

Cyrus E. Tabery, Santa Clara, CA (US);

Shibly S. Ahmed, San Jose, CA (US);

Matthew S. Buynoski, Palo Alto, CA (US);

Srikanteswara Dakshina-Murthy, Wappingers Falls, NY (US);

Zoran Krivokapic, Santa Clara, CA (US);

Haihong Wang, Milpitas, CA (US);

Chih-Yuh Yang, San Jose, CA (US);

Bin Yu, Cupertino, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.


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