The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2006
Filed:
Nov. 24, 2003
Chuan-ping Hou, Yungkong, TW;
Jhi-cherng LU, Taipei, TW;
Kuang-hsin Chen, Jung-li, TW;
Hsun-chih Tsao, Hsin-Chu, TW;
Chuan-Ping Hou, Yungkong, TW;
Jhi-Cherng Lu, Taipei, TW;
Kuang-Hsin Chen, Jung-li, TW;
Hsun-Chih Tsao, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method for forming a field effect transistor includes: forming a conductive region on an isolation layer formed on a substrate, and a cap dielectric layer on the conductive region; forming a sacrificial dielectric layer over the isolation layer and the cap dielectric layer, and on sidewalls of the conductive region; removing a portion of the sacrificial dielectric layer on the cap dielectric layer; removing the cap dielectric layer; removing remaining portions of the sacrificial dielectric layer; forming a gate on the conductive region; and forming source/drain (S/D) regions within the conductive region and adjacent to the gate. A field effect transistor includes a conductive region over an isolation layer formed on a substrate, the conductive region being substantially without undercut at the region within the isolation layer beneath the conductive region; a gate on the conductive region; and S/D regions within the conductive region and adjacent to the gate.