The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2006
Filed:
Oct. 28, 2004
Katsuhiko Iizuka, Gunma, JP;
Kazuo Okada, Ota, JP;
Tomonori Mori, Gunma, JP;
Hiroyuki Dobashi, Gunma, JP;
Hiroyuki Suzuki, Gunma, JP;
Takayoshi Honda, Gunma, JP;
Toshimitsu Taniguchi, Ota, JP;
Katsuhiko Iizuka, Gunma, JP;
Kazuo Okada, Ota, JP;
Tomonori Mori, Gunma, JP;
Hiroyuki Dobashi, Gunma, JP;
Hiroyuki Suzuki, Gunma, JP;
Takayoshi Honda, Gunma, JP;
Toshimitsu Taniguchi, Ota, JP;
Sanyo Electric Co., Ltd., Osaka, JP;
Abstract
An LDD structure and a silicide layer are formed without a reduction in thickness of a silicon substrate or a carbon contamination. Forming a spacer on a sidewall of a gate electrode is performed in two process steps, i.e. dry-etching and wet-etching. Also, a silicon nitride film used as a buffer film in injection of high dose of impurities is removed by wet-etching. As a result, the reduction in thickness of the silicon substrate and the carbon contamination can be prevented. In addition, variation in depth of the high and low impurity concentration regions and silicide forming region with locations on the wafer can be suppressed because of high selection ratio available with the wet-etching.