The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2006
Filed:
Sep. 30, 2003
Xiaowei Yao, Fremont, CA (US);
Tam Nguyen, San Jose, CA (US);
Marc Finot, Palo Alto, CA (US);
Rickie C. Lake, Sunnyvale, CA (US);
Jeffrey A. Bennett, Sunnyvale, CA (US);
Robert Kohler, Zurich, CH;
Xiaowei Yao, Fremont, CA (US);
Tam Nguyen, San Jose, CA (US);
Marc Finot, Palo Alto, CA (US);
Rickie C. Lake, Sunnyvale, CA (US);
Jeffrey A. Bennett, Sunnyvale, CA (US);
Robert Kohler, Zurich, CH;
Intel Corporation, Santa Clara, CA (US);
Abstract
A circuit package includes a base portion and a first metal pattern disposed on a substrate surface. Second and third metal patterns are disposed on another substrate surface, and electrically coupled to first and second vias. The third metal pattern forms a gap to electrically isolate it from the second metal pattern. A circuit package includes a substrate having an opening and a single heat sink positioned in the opening to expose top and bottom surfaces through top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.