The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2006
Filed:
Aug. 19, 2004
Takashi Yamada, Kanagawa-ken, JP;
Hajime Nagano, Kanagawa-ken, JP;
Ichiro Mizushima, Kanagawa-ken, JP;
Tsutomu Sato, Kanagawa-ken, JP;
Hisato Oyamatsu, Kanagawa-ken, JP;
Shinichi Nitta, Kanagawa-ken, JP;
Takashi Yamada, Kanagawa-ken, JP;
Hajime Nagano, Kanagawa-ken, JP;
Ichiro Mizushima, Kanagawa-ken, JP;
Tsutomu Sato, Kanagawa-ken, JP;
Hisato Oyamatsu, Kanagawa-ken, JP;
Shinichi Nitta, Kanagawa-ken, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.