The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2006
Filed:
Feb. 11, 2005
Sheng Feng, Cupertino, CA (US);
Jung-cheun Lien, San Jose, CA (US);
Eddy C. Huang, San Jose, CA (US);
Chung-yuan Sun, San Jose, CA (US);
Tong Liu, San Jose, CA (US);
Naihui Liao, Taipei, TW;
Weidong Xiong, San Jose, CA (US);
Sheng Feng, Cupertino, CA (US);
Jung-Cheun Lien, San Jose, CA (US);
Eddy C. Huang, San Jose, CA (US);
Chung-Yuan Sun, San Jose, CA (US);
Tong Liu, San Jose, CA (US);
Naihui Liao, Taipei, TW;
Weidong Xiong, San Jose, CA (US);
Actel Corporation, Mountain View, CA (US);
Abstract
An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.