The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2006
Filed:
Apr. 27, 2004
Chunghsin Lee, Lynnfield, MA (US);
Jian Zhang, Brookline, MA (US);
Darren M Simonelli, Seabrook, NH (US);
Keith D. Mullins, Plaistow, NH (US);
David A. Wassen, Andover, MA (US);
Chunghsin Lee, Lynnfield, MA (US);
Jian Zhang, Brookline, MA (US);
Darren M Simonelli, Seabrook, NH (US);
Keith D. Mullins, Plaistow, NH (US);
David A. Wassen, Andover, MA (US);
Semigear, Inc., Wakefield, MA (US);
Abstract
An apparatus for the treatment of semiconductor wafers, comprising a supportive frame and a process table arranged on the supportive frame. The process table comprises a stationary upper platen and a stationary lower plate. An intermediate indexing plate is rotatively arranged between the upper platen and the lower plate. At least one wafer support pin is attached to the indexing plate for the support of a wafer by the indexing plate. An upper housing is arranged on the upper platen and an outer lower housing is arranged on the lower plate. A displacable lower isolation chamber is disposed within the outer lower housing, being displacable against the indexing plate to define a treatment module between the upper housing and the lower isolation chamber in which the wafer is treated. A wafer supporting treatment plate is arranged within the lower isolation chamber, for controlled rapid treatment of a wafer within the treatment module.