The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2006
Filed:
Apr. 15, 2003
Allan D. Abrams, Essex Jct., VT (US);
Donald W. Brouillette, St. Albans, VT (US);
Joseph D. Danaher, Hinesburg, VT (US);
Timothy C. Krywanczyk, Essex Jct., VT (US);
Rene A. Lamothe, Saint Albans, VT (US);
Ivan J. Stone, Bakersfield, VT (US);
Matthew R. Whalen, Chelsea, VT (US);
Allan D. Abrams, Essex Jct., VT (US);
Donald W. Brouillette, St. Albans, VT (US);
Joseph D. Danaher, Hinesburg, VT (US);
Timothy C. Krywanczyk, Essex Jct., VT (US);
Rene A. Lamothe, Saint Albans, VT (US);
Ivan J. Stone, Bakersfield, VT (US);
Matthew R. Whalen, Chelsea, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
There is provided a method for making a wafer including the steps of providing a substrate having a first surface, an opposite second surface, and at least one side edge defining a thickness of the substrate, the at least one side edge having a first peripheral region and a second peripheral region adjacent to the first peripheral region. The method includes applying a fluid to the first surface and the first peripheral region of the at least one side edge and removing the opposite second surface and the second peripheral region of the at least one side edge to form a third surface. A semiconductor chip made from the method for making the wafer is also provided.