The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2006
Filed:
Oct. 10, 2003
Toshiaki Iwamatsu, Hyogo, JP;
Yasuo Yamaguchi, Hyogo, JP;
Shigenobu Maeda, Hyogo, JP;
Shoichi Miyamoto, Hyogo, JP;
Akihiko Furukawa, Hyogo, JP;
Yasuo Inoue, Hyogo, JP;
Toshiaki Iwamatsu, Hyogo, JP;
Yasuo Yamaguchi, Hyogo, JP;
Shigenobu Maeda, Hyogo, JP;
Shoichi Miyamoto, Hyogo, JP;
Akihiko Furukawa, Hyogo, JP;
Yasuo Inoue, Hyogo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.