The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2006
Filed:
Jun. 16, 2004
Hiroyuki Kinoshita, Sunnyvale, CA (US);
Yu Sun, Saratoga, CA (US);
Basab Banerjee, Austin, TX (US);
Christopher M. Foster, Austin, TX (US);
John R. Behnke, Austin, TX (US);
Cyrus Tabery, Sunnyvale, CA (US);
Hiroyuki Kinoshita, Sunnyvale, CA (US);
Yu Sun, Saratoga, CA (US);
Basab Banerjee, Austin, TX (US);
Christopher M. Foster, Austin, TX (US);
John R. Behnke, Austin, TX (US);
Cyrus Tabery, Sunnyvale, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.