The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2006

Filed:

Dec. 20, 2002
Applicants:

Gregory M. Chrysler, Chandler, AZ (US);

Paul A. Koning, Chandler, AZ (US);

Saikumar Jayaraman, Chandler, AZ (US);

Makarem A. Hussein, Beaverton, OR (US);

Inventors:

Gregory M. Chrysler, Chandler, AZ (US);

Paul A. Koning, Chandler, AZ (US);

Saikumar Jayaraman, Chandler, AZ (US);

Makarem A. Hussein, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
F35B 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Apparatus and methods in accordance with the present invention utilize thermoelectric cooling (TEC) technology to provide enhanced power distribution and/or dissipation from a microelectronic die and/or microelectronic packages. Individual TEC devices are thermally interconnected with the microelectronic die in a number of placement configurations, including between the microelectronic die and the heat sink, on the integrated heat spreader (IHS) inner surface, and on the IHS outer surface. TEC devices comprise p- and n-type semiconducting material created using similar process as the microcircuits. The TEC devices are located in various regions within or on the microelectronic die, including directly below the microcircuits, on the backside of the microelectronic die, and on a separate substrate of microelectronic die material fabricated apart from the microelectronic die and subsequently thermally coupled to the backside of the microelectronic die.


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