The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2005
Filed:
Sep. 09, 2003
Sarah E. Kim, Portland, OR (US);
Bob Martell, Portland, OR (US);
Dave Ayers, Fremont, CA (US);
R. Scott List, Beaverton, OR (US);
Peter Moon, Portland, OR (US);
Anna M. George, Legal Representative, Phoenix, AZ (US);
Sarah E. Kim, Portland, OR (US);
Bob Martell, Portland, OR (US);
Dave Ayers, Fremont, CA (US);
R. Scott List, Beaverton, OR (US);
Peter Moon, Portland, OR (US);
Anna M. George, legal representative, Phoenix, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile