The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2005

Filed:

Aug. 01, 2001
Applicants:

Chen-fu Chien, Hsinchu, TW;

Kuo-hao Chang, Taichung, TW;

Chih-ping Chen, Hsinchu, TW;

Shun-li Lin, Hsinchu, TW;

Inventors:

Chen-Fu Chien, Hsinchu, TW;

Kuo-Hao Chang, Taichung, TW;

Chih-Ping Chen, Hsinchu, TW;

Shun-Li Lin, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F017/10 ;
U.S. Cl.
CPC ...
Abstract

In the manufacturing of VLSI circuits, production of overlay is a critical step. To obtain a higher resolution and alignment accuracy in microlithographic process, overlay errors must be measured so that overlay errors can be reduced to a tolerable level. This invention provides an overlay error model and a sampling strategy. Utilizing the overlay model and sampling strategy, a device for measuring overlay errors is also designed.


Find Patent Forward Citations

Chien, Chen-Fu. (2005). Overlay error model, sampling strategy and associated equipment for implementation (U.S. Patent No. 6975974). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6975974

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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