The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2005
Filed:
Sep. 17, 2004
Harry Kam Cheng Hong, Melaka, MY;
HU Ah Lek, Melaka, MY;
Santhiran Nadarajah, Melaka, MY;
Sharon Ko Mei Wan, Melaka, MY;
Chan Peng Yeen, Melaka, MY;
Jaime Bayan, Palo Alto, CA (US);
Peter Howard Spalding, Cupertino, CA (US);
Harry Kam Cheng Hong, Melaka, MY;
Hu Ah Lek, Melaka, MY;
Santhiran Nadarajah, Melaka, MY;
Sharon Ko Mei Wan, Melaka, MY;
Chan Peng Yeen, Melaka, MY;
Jaime Bayan, Palo Alto, CA (US);
Peter Howard Spalding, Cupertino, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A panel assembly of packaged integrated circuit devices including a conductive substrate panel having an array of device areas and a plurality of locking passageways. The locking passageways are positioned about an inactive buffer area which surrounds the periphery of the array of device areas. The panel assembly also includes a molded cap that is molded over the topside of the panel to encapsulate the array of device areas and the inactive buffer area. The molded cap includes conforming locking stem portions that extend into each of the locking passageways in a manner locking the molded cap to the substrate panel such that during singulation of the device areas, the molded cap will not separate from the substrate panel at the inactive buffer area. In another aspect of the invention, a method for producing the panel assembly having the locking passageways is described.