The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2005
Filed:
Jun. 24, 2003
Shui-ming Cheng, Hsin-Chu, TW;
Ka-hing Fung, Hsin-Chu, TW;
Yin-pin Wang, Kaohsiung, TW;
Kuan-lun Cheng, Hsin-Chu, TW;
Huan-tsung Huang, Hsin-Chu, TW;
Shui-Ming Cheng, Hsin-Chu, TW;
Ka-Hing Fung, Hsin-Chu, TW;
Yin-Pin Wang, Kaohsiung, TW;
Kuan-Lun Cheng, Hsin-Chu, TW;
Huan-Tsung Huang, Hsin-Chu, TW;
Taiwain Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
The present invention provides methods for manufacturing semiconductor devices. In one embodiment, the method includes forming a gate oxide over a substrate and a gate electrode over the gate oxide. The method also includes implanting impurities into the substrate using the gate electrode as an implant mask to form lightly-doped regions in the substrate. The method further includes forming a first spacer adjacent the gate electrode, and implanting impurities into the substrate and through a portion of the lightly-doped regions using the first spacer as an implant mask to form deep source/drain regions in the substrate. The method still further includes forming a second spacer adjacent the first spacer, implanting impurities into the substrate using the second spacer as an implant mask to form a graded source/drain region in the substrate, and removing the second spacer. Also disclosed is a semiconductor device constructed using the techniques disclosed herein.