The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2005
Filed:
May. 16, 2003
Wen-kai Wan, Hsin-Chu, TW;
Yih-hsiung Lin, Sanchung, TW;
Ming-dai Lei, Hsin-Chu, TW;
Baw-ching Perng, Hsin-Chu, TW;
Cheng-chung Lin, Taipei, TW;
Chia-hui Lin, Hsin-Chu, TW;
Ai-sen Liu, Hsin-Chu, TW;
Wen-Kai Wan, Hsin-Chu, TW;
Yih-Hsiung Lin, Sanchung, TW;
Ming-Dai Lei, Hsin-Chu, TW;
Baw-Ching Perng, Hsin-Chu, TW;
Cheng-Chung Lin, Taipei, TW;
Chia-Hui Lin, Hsin-Chu, TW;
Ai-Sen Liu, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.