The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6953699 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 11, 2005

Filed:

Jul. 27, 2004
Applicants:

Chad A. Cobbley, Boise, ID (US);

John Vannortwick, Kuna, ID (US);

Bret K. Street, Meridian, ID (US);

Tongbi Jiang, Boise, ID (US);

Inventors:

Chad A. Cobbley, Boise, ID (US);

John VanNortwick, Kuna, ID (US);

Bret K. Street, Meridian, ID (US);

Tongbi Jiang, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R031/26 ;
U.S. Cl.
CPC ...
Abstract

Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using 'wet' quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using 'dry' epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.


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