The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2005
Filed:
Jul. 15, 2003
Aritharan Thurairajaratnam, San Jose, CA (US);
Mohan Nagar, Cupertino, CA (US);
Anand Govind, Fremont, CA (US);
Farshad Ghahghahi, Los Gatos, CA (US);
Aritharan Thurairajaratnam, San Jose, CA (US);
Mohan Nagar, Cupertino, CA (US);
Anand Govind, Fremont, CA (US);
Farshad Ghahghahi, Los Gatos, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is connected to a DSO with a fast rise time signal head. During testing, a signal is launched using the DSO into a coaxial cable which is connected to the test head. The launched signal and the reflected signal are captured back by the DSO, and then fed into the tester. Using this data, post processing software is used to obtain the interconnect impedance versus time for the device (i.e., package) under test. The method and apparatus can be used in connection with both Flip Chip and Wire bonded products.