The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2005
Filed:
Nov. 08, 2002
Applicants:
John P. Mccormick, Palo Alto, CA (US);
Ivor G. Barber, Los Gatos, CA (US);
Kumar Nagarajan, San Jose, CA (US);
Inventors:
John P. McCormick, Palo Alto, CA (US);
Ivor G. Barber, Los Gatos, CA (US);
Kumar Nagarajan, San Jose, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L023/34 ; H01L023/48 ; H01L023/52 ;
U.S. Cl.
CPC ...
Abstract
An integrated circuit having electrically conductive vias with a diameter of between about one micron and about fifty microns. Prior art vias have a diameter of between no less than 0.3 microns to no more than 0.8 microns. In this manner, stresses such as those that press down upon the top surface of the integrated circuit can be absorbed by the large vias and transferred past fragile layers, such as low k layers, so that the fragile layers are not damaged by the stresses.