The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2005
Filed:
Dec. 17, 2003
Qi Xiang, San Jose, CA (US);
Jung-suk Goo, Stanford, CA (US);
James N. Pan, Fishkill, NY (US);
Ming Ren Lin, Cupertino, CA (US);
Qi Xiang, San Jose, CA (US);
Jung-Suk Goo, Stanford, CA (US);
James N. Pan, Fishkill, NY (US);
Ming Ren Lin, Cupertino, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
Strained silicon is grown on a dielectric material in a trench in a silicon germanium layer at a channel region of a MOSFET after fabrication of other MOSFET elements using a removable dummy gate process to form an SOI MOSFET. The MOSFET is fabricated with the dummy gate in place, the dummy gate is removed, and a trench is formed in the channel region. Dielectric material is grown in the trench, and strained silicon is then grown from the silicon germanium trench sidewalls to form a strained silicon layer that extends across the dielectric material. The silicon germanium sidewalls impart strain to the strained silicon, and the presence of the dielectric material allows the strained silicon to be grown as a thin fully depleted layer. A replacement gate is then formed by damascene processing.