The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2005
Filed:
Aug. 05, 2003
Tu-anh Tran, Austin, TX (US);
Richard K. Eguchi, Austin, TX (US);
Peter R. Harper, Round Rock, TX (US);
Chu-chung Lee, Round Rock, TX (US);
William M. Williams, Gilbert, AZ (US);
Lois Yong, Austin, TX (US);
Tu-Anh Tran, Austin, TX (US);
Richard K. Eguchi, Austin, TX (US);
Peter R. Harper, Round Rock, TX (US);
Chu-Chung Lee, Round Rock, TX (US);
William M. Williams, Gilbert, AZ (US);
Lois Yong, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.