The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2005

Filed:

Sep. 26, 2003
Applicants:

Sung Soon Park, Seoul, KR;

Sang Jae Jang, Seoul, KR;

Choon Heung Lee, Gyeonggi-do, KR;

Seon Goo Lee, Seoul, KR;

Eun Sook Sohn, Seoul, KR;

Sung Su Park, Seoul, KR;

Inventors:

Sung Soon Park, Seoul, KR;

Sang Jae Jang, Seoul, KR;

Choon Heung Lee, Gyeonggi-do, KR;

Seon Goo Lee, Seoul, KR;

Eun Sook Sohn, Seoul, KR;

Sung Su Park, Seoul, KR;

Assignee:

Amkor Technology, Inc., Chandler, AZ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L023/48 ;
U.S. Cl.
CPC ...
Abstract

An electrical substrate useful for semiconductor packages is disclosed. The electrical substrate includes a core insulative layer. A first surface of the insulative layer has circuit patterns thereon. Some of the circuit patterns are stepped in their heights from the first surface, in that a first subportion of the circuit pattern, including a ball land, extends further from the first surface than a second subportion of the same circuit pattern, and also extends further from the first surface than a ball land of other circuit patterns. Accordingly, solder balls fused to the ball lands of the stepped circuit patterns extend further from the first surface than same-size solder balls fused to the ball lands of the non-stepped circuit patterns, thereby circumventing electrical connectivity problems that may arise from warpage of the electrical substrate.


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