The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6936529 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 30, 2005

Filed:

Dec. 02, 2003
Applicants:

Kwan-yong Lim, Ichon-shi, KR;

Heung-jae Cho, Ichon-shi, KR;

Jung-ho Lee, Ichon-shi, KR;

Se-aug Jang, Ichon-shi, KR;

Yong-soo Kim, Ichon-shi, KR;

Byung-seop Hong, Ichon-shi, KR;

Jae-geun OH, Ichon-shi, KR;

Hong-seon Yang, Ichon-shi, KR;

Hyun-chul Sohn, Ichon-shi, KR;

Inventors:

Kwan-Yong Lim, Ichon-shi, KR;

Heung-Jae Cho, Ichon-shi, KR;

Jung-Ho Lee, Ichon-shi, KR;

Se-Aug Jang, Ichon-shi, KR;

Yong-Soo Kim, Ichon-shi, KR;

Byung-Seop Hong, Ichon-shi, KR;

Jae-Geun Oh, Ichon-shi, KR;

Hong-Seon Yang, Ichon-shi, KR;

Hyun-Chul Sohn, Ichon-shi, KR;

Assignee:

Hynix Semiconductor Inc., Ichon-shi, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/4763 ; H01L021/3205 ;
U.S. Cl.
CPC ...
Abstract

The present invention relates to a method for fabricating a gate electrode of a semiconductor device with a double hard mask capable of preventing an abnormal oxidation of a metal layer included in the gate electrode and suppressing stress generation. The method includes the steps of: forming a gate insulation layer on a substrate; forming a gate layer structure containing at least a metal layer on the gate insulation layer; forming a hard mask oxide layer on the gate layer structure at a temperature lower than an oxidation temperature of the metal layer; forming a hard mask nitride layer on the hard mask oxide layer; patterning the hard mask oxide layer and the hard mask nitride layer as a double hard mask for forming the gate electrode; and forming the gate electrode by etching the gate layer structure with use of the double hard mask as an etch mask.


Find Patent Forward Citations

Lim, Kwan-Yong. (2005). Method for fabricating gate-electrode of semiconductor device with use of hard mask (U.S. Patent No. 6936529). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6936529

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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