The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2005

Filed:

Aug. 26, 2003
Applicants:

Noriyoshi Shimizu, Nagano, JP;

Akio Rokugawa, Nagano, JP;

Takahiro Iijima, Nagano, JP;

Inventors:

Noriyoshi Shimizu, Nagano, JP;

Akio Rokugawa, Nagano, JP;

Takahiro Iijima, Nagano, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L023/48 ; H01L023/52 ; H01L029/40 ;
U.S. Cl.
CPC ...
Abstract

A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.


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