The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2005
Filed:
Jun. 24, 2002
Sammy Mok, Cupertino, CA (US);
Fu Chiung Chong, Saratoga, CA (US);
Frank John Swiatowiec, San Jose, CA (US);
Syamal Kumar Lahiri, Milpitas, CA (US);
Joseph Michael Haemer, San Jose, CA (US);
Sammy Mok, Cupertino, CA (US);
Fu Chiung Chong, Saratoga, CA (US);
Frank John Swiatowiec, San Jose, CA (US);
Syamal Kumar Lahiri, Milpitas, CA (US);
Joseph Michael Haemer, San Jose, CA (US);
NanoNexus, Inc., Fremont, CA (US);
Abstract
Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a compliant carrier structure, such as a decal or screen, which is adhesively attached to the probe chip substrate.