The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2005
Filed:
Feb. 13, 2003
Ching-hui MA, Tainan, TW;
Chao-cheng Chen, Tainan, TW;
Tsang-jiuh Wu, Taichung, TW;
Hui-chang Yu, Hsin-chu, TW;
Hun-jan Tao, Hsinchu, TW;
Ching-Hui Ma, Tainan, TW;
Chao-Cheng Chen, Tainan, TW;
Tsang-Jiuh Wu, Taichung, TW;
Hui-Chang Yu, Hsin-chu, TW;
Hun-Jan Tao, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method of reducing a charge on a substrate to prevent an arcing incident in a subsequent etch process is described. A patterned substrate is fastened to a chuck in a process chamber. A discharge process is performed that includes the three steps of (a) coupling the chuck to a 0 volt connection, (b) generating a plasma, and (c) coupling the chuck to a high voltage connection. The three steps are carried out in any sequence. An inert gas or an inert gas and an etching gas are flowed into the chamber during the discharge sequence. Alternatively, a fluorocarbon CFHor a fluorocarbon and a gas such as O, H, N, NO, CO, CO, He or Ar is flowed into the chamber during the discharge sequence. The method is compatible with batch or single wafer processes and is extendable to etching low k dielectric layers with poor thermal conductivity.