The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2005
Filed:
Mar. 28, 2002
Johanna M. Swan, Scottsdale, AZ (US);
Ravi V. Mahajan, Tempe, AZ (US);
Bala Natarajan, Phoenix, AZ (US);
Johanna M. Swan, Scottsdale, AZ (US);
Ravi V. Mahajan, Tempe, AZ (US);
Bala Natarajan, Phoenix, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
The opening is initially fabricated in an upper surface of a wafer substrate, which allows for the use of alignment features on the upper surface of the wafer substrate. The openings are then filled with plugs. An integrated circuit is then manufactured over the upper surface of the substrate and the plugs. The plugs are located below the integrated circuit and do not take up 'real estate' reserved for metal layers of the integrated circuit. A carrier is then bonded to an upper surface of the integrated circuit, whereafter a lower portion of the wafer substrate is removed in a grinding and etching operation. The plugs are then removed through a lower surface of the wafer substrate, whereafter the openings are filled with conductive members in a plating operation. A metal redistribution layer can be formed on a lower surface of the wafer substrate, because the carrier provides sufficient rigidity.