The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2005

Filed:

May. 30, 2003
Applicants:

Chih-jung NI, Hsinchu, TW;

Chung-ming Chu, Tainan, TW;

Tu-hao Yu, Hua-Lien Hsien, TW;

Kuo-chen Wang, Chiai, TW;

Wen-shun Lo, Hsinchu, TW;

Haochieh Liu, Taipei, TW;

Inventors:

Chih-Jung Ni, Hsinchu, TW;

Chung-Ming Chu, Tainan, TW;

Tu-Hao Yu, Hua-Lien Hsien, TW;

Kuo-Chen Wang, Chiai, TW;

Wen-Shun Lo, Hsinchu, TW;

Haochieh Liu, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L029/788 ;
U.S. Cl.
CPC ...
Abstract

A flash memory cell is described, including at least a substrate, a tunnel oxide layer, a floating gate, an insulating layer, a control gate and an inter-gate dielectric layer. The tunnel oxide layer is disposed on the substrate. The floating gate is disposed on the tunnel oxide layer, and is constituted by a first conductive layer on the tunnel oxide layer and a second conductive layer on the first conductive layer. The second conductive layer has a bottom lower than the top surface of the first conductive layer, and has a bowl-like cross section. The insulating layer is disposed between the floating gates, and each control gate is disposed on a floating gate with an inter-gate dielectric layer between them.


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