The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2005

Filed:

Jul. 30, 2003
Applicants:

Emanual I. Cooper, Scarsdale, NY (US);

John M. Cotte, New Fairfield, CT (US);

Lisa A. Fanti, Hopewell Junction, NY (US);

David E. Eichstadt, Noth Salem, NY (US);

Stephen J. Kilpatrick, Lagrangeville, NY (US);

Henry A. Nye, Iii, Brookfield, CT (US);

Donna S. Zupanski-nielsen, Yorktown Heights, NY (US);

Inventors:

Emanual I. Cooper, Scarsdale, NY (US);

John M. Cotte, New Fairfield, CT (US);

Lisa A. Fanti, Hopewell Junction, NY (US);

David E. Eichstadt, Noth Salem, NY (US);

Stephen J. Kilpatrick, Lagrangeville, NY (US);

Henry A. Nye, III, Brookfield, CT (US);

Donna S. Zupanski-Nielsen, Yorktown Heights, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/461 ;
U.S. Cl.
CPC ...
Abstract

A method is provided for removing exposed seed layers in the fabrication of solder interconnects on electronic components such as semiconductor wafers without damaging the interconnects or underlying wafer substrate and with a high wafer yield. The solder interconnects are lead free or substantially lead free and typically contain Sn. An oxalic acid solution is used to contact the wafer after an etching step to remove part of the seed layer. The seed layer is typically a Cu containing layer with a lower barrier layer containing barrier metals such as Ti, Ta and W. The lower barrier layer remains after the etch and the oxalic acid solution inhibits the formation of Sn compounds on the barrier layer surface which compounds may mask the barrier layer and the barrier layer etchant resulting in incomplete barrier layer removal on the wafer surface. Any residual conductive barrier layer can cause shorts and other wafer problems and result in a lower wafer yield. An electroetch is preferred to remove the portion of the seed layer overlying the lower barrier layer.


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