The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2005
Filed:
Apr. 21, 2003
Munir D. Naeem, Poughkeepsie, NY (US);
Hiroyuki Akatsu, Yorktown Heights, NY (US);
Byeong Kim, Lagrangeville, NY (US);
Rolf Weis, Dresden, DE;
David Mark Dobuzinksy, New Windsor, NY (US);
Johnathan E. Faltermeier, Lagrangeville, NY (US);
Munir D. Naeem, Poughkeepsie, NY (US);
Hiroyuki Akatsu, Yorktown Heights, NY (US);
Byeong Kim, Lagrangeville, NY (US);
Rolf Weis, Dresden, DE;
David Mark Dobuzinksy, New Windsor, NY (US);
Johnathan E. Faltermeier, Lagrangeville, NY (US);
Infineon Technologies AG, Munich, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.