The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2005
Filed:
Jul. 16, 2002
Shigeki Ohbayashi, Tokyo, JP;
Yoshiyuki Ishigaki, Tokyo, JP;
Takahiro Yokoyama, Tokyo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A CMOS-SRAM has a plurality of full CMOS type memory cells () and a capacity plate (). The memory cells () are two-dimensionally arranged in the row direction and in the column direction. The capacity plateadds an additional capacity to nodes NDand NDfor storing data in order to reduce soft errors. The capacity plate () is common with the plurality of memory cells (). The capacity plates () are separated by every column, that is in the row direction. The capacity plate () is connected to a power voltage line VDD so as to simplify the voltage supplying system. When a stand-by failure occurs in the memory cell () of a certain column, the memory cell () is replaced with a redundant memory cell.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile