The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6877118 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 05, 2005

Filed:

Apr. 27, 2001
Applicants:

Hiromi Oshima, Tokyo, JP;

Noboru Okino, Tokyo, JP;

Yasuhiro Kawata, Tokyo, JP;

Inventors:

Hiromi Oshima, Tokyo, JP;

Noboru Okino, Tokyo, JP;

Yasuhiro Kawata, Tokyo, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C029/00 ;
U.S. Cl.
CPC ...
Abstract

A memory testing method and apparatus are provided, which can test in short time a flash memory. In case of testing a flash memory having block function, in a memory testing method and apparatus in which a predetermined logical value is written in memory cells constituting each of blocks of the memory, the written logical value is read out from the memory cells to compare it with an expected value, and a decision that, when the read-out logical value and the expected value do not coincide with each other, such memory cell is a failure memory cell, a decision is rendered that, when the number of failure memory cells in each block reaches a predetermined number, such block is a bad block, and the test of such block is stopped. In addition, a decision is rendered that, when the number of failure memory cells on the same address line reaches a predetermined number, such address line is a bad address line, and after such decision has rendered, the test of memory cells on the bad address line is substantially not effected.


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Oshima, Hiromi. (2005). Memory testing method and memory testing apparatus (U.S. Patent No. 6877118). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6877118

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