The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2005

Filed:

Jun. 17, 2002
Applicants:

Edmond Abrahamians, Fremont, CA (US);

Igor Kravtsov, Mountain View, CA (US);

Herbert Wayne Owens, Jr., San Jose, CA (US);

William Jefferson Stone, Iii, Santa Cruz, CA (US);

Vladimir Volovich, Mountain View, CA (US);

Yakov Keyfes, San Francisco, CA (US);

Inventors:

Edmond Abrahamians, Fremont, CA (US);

Igor Kravtsov, Mountain View, CA (US);

Herbert Wayne Owens, Jr., San Jose, CA (US);

William Jefferson Stone, III, Santa Cruz, CA (US);

Vladimir Volovich, Mountain View, CA (US);

Yakov Keyfes, San Francisco, CA (US);

Assignee:

Accretech USA, Inc., Bloomfield Hills, MI (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B24B049/00 ;
U.S. Cl.
CPC ...
Abstract

An apparatus and method is provided for polishing work pieces such as semiconductor wafers. The apparatus includes a variable number of independent heads, platensand polishing units. This polishing apparatus belongs to a group of polishing machines with wafers attached to the same headsthrough all polishing steps without undesirable reloading from one headto another between polishing steps. Each independent headis automatically coupled to and decoupled from any of the polishing unitsto optimize throughput and provide flexibility in accommodating different polishing processes. A head transfer subsystemprovides an independent means of transfer for each head, thus an infinite number of contemporaneous or overlapping polishing cycles can be completed on multiple wafers resulting in maximum processing throughput.


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