The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2005

Filed:

Sep. 22, 2003
Applicants:

Dureseti Chidambarrao, Weston, CT (US);

Omer H. Dokumaci, Wappingers Falls, NY (US);

Rajesh Rengarajan, Wappingers Falls, NY (US);

An L. Steegen, Stamford, CT (US);

Inventors:

Dureseti Chidambarrao, Weston, CT (US);

Omer H. Dokumaci, Wappingers Falls, NY (US);

Rajesh Rengarajan, Wappingers Falls, NY (US);

An L. Steegen, Stamford, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/38 ; H01L021/28 ;
U.S. Cl.
CPC ...
Abstract

A method for manufacturing an integrated circuit having a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor on a semiconductor wafer by creating a spacer having a first width for the n-type field effect transistor and creating a spacer having a second width for the p-type field effect transistor, the first width being greater than the second width and depositing silicide material on the semiconductor wafer such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor and compressive stresses are formed within a channel of the p-type field effect transistor.


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