The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2005
Filed:
Jan. 15, 2004
Yuan-hung Liu, Shin-Chu, TW;
Yeur-luen Tu, Taichung, TW;
Chin-ta Wu, Hsinchu, TW;
Tsung-hsun Huang, Taipei, TW;
Hsiu Ouyang, Taipei, TW;
Chi-hsin Lo, Jhubei, TW;
Chia-shiung Tsai, Hsin-Chu, TW;
Yuan-Hung Liu, Shin-Chu, TW;
Yeur-Luen Tu, Taichung, TW;
Chin-Ta Wu, Hsinchu, TW;
Tsung-Hsun Huang, Taipei, TW;
Hsiu Ouyang, Taipei, TW;
Chi-Hsin Lo, Jhubei, TW;
Chia-Shiung Tsai, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Hsinchu, TW;
Abstract
A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer. Then etching: away the exposed portions of the conductive layer over the substrate; and through at least a portion of the thinned oxide layer and into the exposed underlying portion of the conductive layer to expose a portion of the inchoate split-gate flash memory structure and to form the word-line spacers adjacent the inchoate split-gate flash memory structure.