The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2005

Filed:

Mar. 20, 2003
Applicants:

Li-te S. Lin, Hsin-Chu, TW;

Yui Wang, Taichung, TW;

Ming-ching Chang, Taipei, TW;

Li-shung Chen, Hsinchu, TW;

Huain-jelin Lin, Hsin-Chu, TW;

Yuan-hong Chin, Taipei, TW;

Hong-yuan Tao, Hsinchu, TW;

Inventors:

Li-Te S. Lin, Hsin-Chu, TW;

Yui Wang, Taichung, TW;

Ming-Ching Chang, Taipei, TW;

Li-Shung Chen, Hsinchu, TW;

Huain-Jelin Lin, Hsin-Chu, TW;

Yuan-Hong Chin, Taipei, TW;

Hong-Yuan Tao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/302 ;
U.S. Cl.
CPC ...
Abstract

A method for compensating for CD variations across a semiconductor process wafer surface in a plasma etching process including providing a semiconductor wafer having a process surface including photolithographically developed features imaged from a photomask; determining a first dimensional variation of the features with respect to corresponding photomask dimensions along at least one wafer surface direction to determine a first levelness of the process surface; determining gas flow parameters in a plasma reactor for a plasma etching process required to approach a level process surface by reference to an archive of previous plasma etching process parameters carried out in the plasma reactor; carrying out the plasma etching process in the plasma rector according to the determined gas flow parameters; and, determining a second dimensional variation of the features along the at least one wafer surface direction to determine a second levelness of the process surface.


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