The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2005
Filed:
Dec. 18, 2002
Ching-kwun Huang, Yongho, TW;
Chih-chang Chen, Hsin-Chu, TW;
Hsien-chih Peng, Hsin-Chu, TW;
Pin-shyne Chin, Hsin-Chu, TW;
Ching-Kwun Huang, Yongho, TW;
Chih-Chang Chen, Hsin-Chu, TW;
Hsien-Chih Peng, Hsin-Chu, TW;
Pin-Shyne Chin, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company Ltd., Hsin-Chu, TW;
Abstract
A method to fabricate a 1T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.