The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2005

Filed:

Aug. 10, 2001
Applicants:

Mohamed N. Darwish, Campbell, CA (US);

Frederick P. Giles, San Jose, CA (US);

Kam Hong Lui, Santa Clara, CA (US);

Kuo-in Chen, Los Altos, CA (US);

Kyle Terrill, Santa Clara, CA (US);

Inventors:

Mohamed N. Darwish, Campbell, CA (US);

Frederick P. Giles, San Jose, CA (US);

Kam Hong Lui, Santa Clara, CA (US);

Kuo-In Chen, Los Altos, CA (US);

Kyle Terrill, Santa Clara, CA (US);

Assignee:

Siliconix incorporated, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2976 ; H01L 2994 ; H01L 31062 ; H01L 31113 ; H01L 31119 ;
U.S. Cl.
CPC ...
Abstract

Trench MOSFETs including active corner regions and a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such MOSFETs. In an exemplary embodiment, the trench MOSFET includes a thick insulative layer centrally located at the bottom of the trench. A thin gate insulative layer lines the sidewall and a peripheral portion of the bottom surface of the trench. A gate fills the trench, adjacent to the gate insulative layer. The gate is adjacent to the sides and top of the thick insulative layer. The thick insulative layer separates the gate from the drain conductive region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications.


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