The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2004

Filed:

Dec. 12, 2001
Applicant:
Inventors:

Tso-Hung Fan, Taipei Hsien, TW;

Yen-Hung Yeh, Taoyuan Hsien, TW;

Kwang-Yang Chan, Hsinchu, TW;

Mu-Yi Liu, Taichung, TW;

Tao-Cheng Lu, Kaoshiung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/604 ; G11C 5/06 ; G06F 1/200 ;
U.S. Cl.
CPC ...
G11C 1/604 ; G11C 5/06 ; G06F 1/200 ;
Abstract

A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.


Find Patent Forward Citations

Loading…